1. Field of the Invention
The present invention relates to a data processing apparatus and control method thereof and, more particularly, to a technique for reducing power consumption while suppressing the processing response performance of multi-core processing from lowering.
2. Description of the Related Art
As described in Japanese Patent Laid-Open No. 2006-285719, in a ring type bus connection system having a plurality of processing execution modules, the respective processing execution modules include local memories to avoid occurrence of access wait statuses to the memories. With this arrangement, data processing can be efficiently executed with small power consumption.
However, in the arrangement of Japanese Patent Laid-Open No. 2006-285719, when a processing response time difference is generated between the processing execution modules, a module having a shorter processing response time completes processing earlier than a module having a longer processing response time. In this case, for example, generation of a leakage current in an idle time results in wasteful power consumption. Also, in the arrangement of Japanese Patent Laid-Open No. 2006-285719, in order to attain a further power consumption reduction, the operating frequency of the overall system has to be lowered. However, when the operating frequency of the overall system is lowered, the performance of the entire system is also lowered.